Transistor-Level Fault Detection Based on Power Consumption

Gate level fault models, although simplify test pattern generation and permit to gather diierent faults into equivalence classes, in some case are unrealistic and may lead to test invalidation since they do not take into account the physical aspects of the problem. In general all the faults that may aaect a circuit may be divided into shorts and opens, a logic test may not be able to detect all the possible shorts and opens. The detectability or not of a fault is strictly tied to physical factors such as layout structure and technology used, since these parameters may determine whether the output of a faulty gate is indeterminate or not. The presence of indeterminate logic values at a faulty gate output is an hard-to-solve problem in high level test generation, because, if the faulty gate has multiple fanouts, it is not guaranteed the fault to propagate along all the fanouts. The necessity of a test strategy closer to the physical nature of a fault has led to the exploitation of current monitoring as a means to test a faulty circuit. In fact it has been found that the quiescent currents of a faulty circuit are at least two or three times the ones of a fault-free circuit. Thus a faulty circuit has a power consumption bigger than a fault-free circuit. A current test has the advantage that a test pattern may be easily generated for all the multiple physical faults that are current-testable, on the other hand it does not detect all the possible physical faults and it is slowlier than a voltage test since we have to wait for the transient currents to settle, before performing the measurement. Anyway, the scientiic community seems to agree with the idea that the testing strategy that ooers the best fault coverage is a combined current and voltage test. The measurement of the faulty currents is performed by an analog sensor that may be placed on or oo-chip. Built-in current sensors lead to a faster test but they also complicate and slow down the circuit to be tested. This problems may be avoided using an external sensor, anyway such sensors slow down the test. In this paper we perform a study on several types of physical faults, analyzing the eeect of the fault on the power consumption of the gate. Almost in every case analyzed we have found an increase in the quiescent …